1. Field of the Invention
The present invention relates to synchronization circuits and synchronization techniques. More specifically, the present invention relates to a synchronization circuit that synchronizes different timing domains based on state variables.
2. Related Art
Many integrated circuits contain different functional blocks that operate at different speeds. As a consequence, these integrated circuits may include different timing domains. Because the different functional blocks in these integrated circuits often interact with each other, it is typically useful to synchronize or lock the clock signals in the different timing domains. For example, the clock signals from different timing domains may be synchronized using a phase-locked loop.
However, existing synchronization techniques typically bring the frequency and the phase of the clock signals into lock in a nonlinear or an unpredictable manner. For example, the frequency and the phase of the clock signals being locked are often a nonlinear function of time.
This nonlinear or erratic behavior of the clock signals during synchronizing can cause problems in a variety of applications. For example, if clock signals in a media transport system have nonlinear variations while they are being locked, there may be undesirable transients in resulting audio signals that users can perceive. More generally, nonlinear or erratic variations in clock signals during synchronization can adversely impact data transport in a series of cascaded circuits.
Hence, what is needed are synchronization circuits and techniques that overcome the problems listed above.